The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 23, 2012

Filed:

Jan. 22, 2009
Applicants:

Ryuji Kyushima, Hamamatsu, JP;

Harumichi Mori, Hamamatsu, JP;

Junichi Sawada, Hamamatsu, JP;

Kazuki Fujita, Hamamatsu, JP;

Masahiko Honda, Hamamatsu, JP;

Inventors:

Ryuji Kyushima, Hamamatsu, JP;

Harumichi Mori, Hamamatsu, JP;

Junichi Sawada, Hamamatsu, JP;

Kazuki Fujita, Hamamatsu, JP;

Masahiko Honda, Hamamatsu, JP;

Assignee:

Hamamatsu Photonics K.K., Hamamatsu-shi, Shizuoka, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 9/64 (2006.01); H04N 3/335 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a solid-state imaging device, etc., which makes it possible to obtain an image with higher resolution by properly correcting pixel data even when any one of row selecting wirings is disconnected. A solid-state imaging device () comprises a photodetecting section (), a signal reading-out section (), a controlling section (), and a correction processing section (). In the photodetecting section (), M×N pixel portions Pto Pare two-dimensionally arrayed in a matrix of M rows and N columns, and each of the pixel portions Pto Pincludes a photodiode and a reading-out switch. Charges generated in each pixel portion Pare inputted into an integrating circuit Sthrough a reading-out wiring L, and a voltage value corresponding to the amount of charges is outputted from the integrating circuit S. The voltage value from the integrating circuit Sis outputted to an output wiring Lthrough a holding circuit H. In the correction processing section (), correction processing is applied to frame data repeatedly outputted from the signal reading-out section (), and the frame data after correction is outputted.


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