The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Apr. 22, 2010
Hiroyuki Kutsukake, Yokohama, JP;
Takayuki Toba, Yokohama, JP;
Yoshiko Kato, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Haruhiko Koyama, Yokohama, JP;
Hiroyuki Kutsukake, Yokohama, JP;
Takayuki Toba, Yokohama, JP;
Yoshiko Kato, Yokohama, JP;
Kenji Gomikawa, Yokohama, JP;
Haruhiko Koyama, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.