The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Feb. 11, 2010
Dong-chul Yoo, Seongnam-si, KR;
Eun-ha Lee, Seoul, KR;
Byong-ju Kim, Suwon-si, KR;
Hyung-ik Lee, Suwon-si, KR;
Sung Heo, Suwon-si, KR;
Han-mei Choi, Seoul, KR;
Chan-hee Park, Pocheon-si, KR;
Ki-hyun Hwang, Seongnam-si, KR;
Dong-Chul Yoo, Seongnam-si, KR;
Eun-Ha Lee, Seoul, KR;
Byong-Ju Kim, Suwon-si, KR;
Hyung-Ik Lee, Suwon-si, KR;
Sung Heo, Suwon-si, KR;
Han-Mei Choi, Seoul, KR;
Chan-Hee Park, Pocheon-si, KR;
Ki-Hyun Hwang, Seongnam-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;
Abstract
A semiconductor integrated circuit device is provided. The semiconductor integrated circuit device includes a plurality of isolation regions which are formed within a semiconductor substrate and define active regions. A tunnel layer and a trap seed layer are formed in each of the active regions and are sequentially stacked between the isolation regions. A trap layer is formed on the trap seed layer and protrudes further than a top surface of each of the isolation regions. A blocking layer is formed on the trap layer. A gate electrode is formed on the blocking layer.