The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Nov. 06, 2007
Kerry Bernstein, Underhill, VT (US);
Jerome L. Cann, Jericho, VT (US);
Christopher M. Durham, Round Rock, TX (US);
Paul D. Kartschoke, Williston, VT (US);
Peter J. Klim, Austin, TX (US);
Donald L. Wheater, Hinesburg, VT (US);
Kerry Bernstein, Underhill, VT (US);
Jerome L. Cann, Jericho, VT (US);
Christopher M. Durham, Round Rock, TX (US);
Paul D. Kartschoke, Williston, VT (US);
Peter J. Klim, Austin, TX (US);
Donald L. Wheater, Hinesburg, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A plurality of peripheral test structure substrate (PTSS) through vias is formed within a peripheral test structure substrate. A peripheral test structure layer and at least one functional layer are formed on one side of the plurality of the PTSS through vias. The other side of the plurality of the PTSS through vias is exposed throughout fabrication of the peripheral test structure layer and the at least one functional layer to provide access points for testing functionality of the various layers throughout the manufacturing sequence. Cbonding may be performed after manufacture of all of the at least one functional layer is completed. A 3D assembly carrier or a Ccarrier substrate is not required since the peripheral test structure substrate has sufficient mechanical strength to support the peripheral test structure layer and the at least one functional layer.