The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 23, 2012
Filed:
Apr. 06, 2010
Masaru Kadoshima, Tokyo, JP;
Shinsuke Sakashita, Tokyo, JP;
Takaaki Kawahara, Tokyo, JP;
Jiro Yugami, Tokyo, JP;
Masaru Kadoshima, Tokyo, JP;
Shinsuke Sakashita, Tokyo, JP;
Takaaki Kawahara, Tokyo, JP;
Jiro Yugami, Tokyo, JP;
Renesas Electronics Corporation, Kanagawa, JP;
Abstract
To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film. Then, after removing the unreacted threshold adjustment film and the metal nitride film, metal gate electrodes are formed in the nMIS formation region and the pMIS formation region.