Method for reducing surface area of pad limited semiconductor die layout

Abstract

A method for reducing a surface area of a pad limited semiconductor die layout includes choosing an outer die pad row from a group of outer die pad rows on the semiconductor die, each of the outer die pad rows being adjacent an edge of the semiconductor die. Next, the method performs selecting, from the outer die pad row, a common die pad group with die pads that are arranged to be electrically connected to an external connection pad. The method then performs repositioning a subgroup of the common die pad group on an inner die pad row, the inner pad row being adjacent the outer die pad row. After he repositioning there is performed a step of adjusting positions of at least some of the remaining pads in the outer die pad row thereby reducing an overall length of the outer die pad row. The method then provides for repeating the above steps until the surface area of a pad limited semiconductor die cannot be reduced any further by the step of adjusting positions or until every common die pad group, on every one of the outer die pad rows, has been selected by the selecting step.