The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2012

Filed:

Jul. 15, 2009
Applicants:

Hayato Higuchi, Kawasaki, JP;

Shinichi Sutou, Kawasaki, JP;

Tsuguchika Tabaru, Kawasaki, JP;

Manabu Matsuyama, Kawasaki, JP;

Ryuichi Ohzeki, Kawasaki, JP;

Toshihiro Suzuki, Kawasaki, JP;

Inventors:

Hayato Higuchi, Kawasaki, JP;

Shinichi Sutou, Kawasaki, JP;

Tsuguchika Tabaru, Kawasaki, JP;

Manabu Matsuyama, Kawasaki, JP;

Ryuichi Ohzeki, Kawasaki, JP;

Toshihiro Suzuki, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A data conversion apparatus for converting circuit description related to a dynamically-reconfigurable circuit to circuit configuration information, the data conversion apparatus includes a first generation section that generates a data flow graph from the circuit description; a segment count determining section that determines a number of segments for segmenting the data flow graph generated by the first generation section; a virtual circuit creating section that creates a virtual circuit that has as many resources of the dynamically-reconfigurable circuit as the number of the resources multiplied by the number of segments determined by the segment count determining section; a second generation section that generates, from the circuit description, a data flow graph corresponding to the virtual circuit created by the virtual circuit creating section; and a conversion section that allocates and adjusts the resources of the virtual circuit in accordance with the data flow graph.


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