The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2012

Filed:

May. 04, 2011
Applicants:

Chulmin Jung, Eden Prairie, MN (US);

Dadi Setiadi, Edina, MN (US);

Youngpil Kim, Eden Prairie, MN (US);

Harry Hongyue Liu, Maple Grove, MN (US);

Hyung-kyu Lee, Edina, MN (US);

Inventors:

Chulmin Jung, Eden Prairie, MN (US);

Dadi Setiadi, Edina, MN (US);

YoungPil Kim, Eden Prairie, MN (US);

Harry Hongyue Liu, Maple Grove, MN (US);

Hyung-Kyu Lee, Edina, MN (US);

Assignee:

Seagate Technology LLC, Scotts Valley, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 8/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Apparatus and method for decoding addresses of control lines in a semiconductor device, such as a solid state memory (SSM). In accordance with some embodiments, a switching circuit includes an array of switching devices coupled to 2output lines and M input lines, wherein M and N are respective non-zero integers and each output line has a unique N-bit address. A decoder circuit coupled to the switching circuit divides the N-bit address for a selected output line into a plurality of multi-bit subgroup addresses, and asserts the M input lines in relation to respective bit values of said subgroup addresses to apply a first voltage to the selected output line and to concurrently apply a second voltage to the remaining 2−1 output lines.


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