The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 16, 2012

Filed:

Dec. 28, 2007
Applicants:

Hong Sung Song, Gyeongsangbuk-do, KR;

Woong Ki Min, Daegu, KR;

Byung Jin Choi, Gyeongsangbuk-do, KR;

Dong Hoon Cha, Gyeongsangbuk-do, KR;

Su Hyuk Jang, Daegu, KR;

Inventors:

Hong Sung Song, Gyeongsangbuk-do, KR;

Woong Ki Min, Daegu, KR;

Byung Jin Choi, Gyeongsangbuk-do, KR;

Dong Hoon Cha, Gyeongsangbuk-do, KR;

Su Hyuk Jang, Daegu, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01);
U.S. Cl.
CPC ...
Abstract

A disclosed display includes a display panel including a first group of data lines and second group of data lines, a plurality of gate lines crossing the first and a second groups of data lines, and a plurality of picture cells arranged in a matrix. The display also includes a first source PCB coupled to first data integrated circuits (ICs) to supply first data voltages to the first group of data lines and a second source PCB coupled to second data ICs to supply second data voltages to the second group of data lines. The display further includes a timing controller having a single output port with a plurality of output pins which are configured to output video data to both the first and second data ICs, and to output a timing control signal to control both the first and second data ICs. In addition, the display includes a first connection cable coupling the single output port of the timing controller to at least one of the first and second source PCBs to transmit the video data and the timing control signal from the timing controller to the at least one of the first and second source PCBs. The first data ICs and second data ICs are configured to generate the first and second data voltages, respectively, based on the video data and the timing control signal.


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