The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 16, 2012
Filed:
May. 05, 2006
Kenneth W. Fernald, Austin, TX (US);
Milton Martin Hood, Jr., Austin, TX (US);
Kris P. Dehnel, Cedar Park, TX (US);
Aaron Michael Shreeve, Austin, TX (US);
Kenneth W. Fernald, Austin, TX (US);
Milton Martin Hood, Jr., Austin, TX (US);
Kris P. Dehnel, Cedar Park, TX (US);
Aaron Michael Shreeve, Austin, TX (US);
Zilker Labs, Inc., Austin, TX (US);
Abstract
Embodiments of a system and method to control the overlap times—and deadtime delays—in power converters may support both overlapping and non-overlapping gate control signals, which may provide improved efficiency optimization across a wider range of applications. Various embodiments may be configured to provide careful partitioning between hardware implementation and software control, in order to better accommodate microprocessor-based power converters. Software algorithms may be used to avoid restrictions such as high gate impedance and changing load effects, and protection against errant operation may be provided using an overlap watchdog circuit. Various control circuits may be operated according to one or more algorithms configured to optimize both the HS-to-LS and LS-to-HS deadtime delays for obtaining minimum possible PWM duty cycle values to achieve improved power efficiency.