The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2012

Filed:

Dec. 09, 2008
Applicants:

Holger Wetter, Weil im Schoenbuch, DE;

Maarten Boersma, Holzgerlingen, DE;

Wilhelm Haller, Remshalden, DE;

Armin Windschiegl, Weil im Schoenbuch, DE;

Inventors:

Holger Wetter, Weil im Schoenbuch, DE;

Maarten Boersma, Holzgerlingen, DE;

Wilhelm Haller, Remshalden, DE;

Armin Windschiegl, Weil im Schoenbuch, DE;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A system for creating layout and wiring diagrams for an integrated circuit (IC) includes a placement engine configured to receive a hierarchical schematic and to create a placed layout. The system also includes a flat layout engine configured to receive the hierarchical schematic and to create a flat layout and a back annotation engine coupled to the placement engine and the flat layout engine, the back annotation engine configured to receive the hierarchical placed layout and the flat unplaced layout and to create a flat placed layout there from.


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