The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Mar. 24, 2010
Tetsuo Hironaka, Hiroshima, JP;
Kazuya Tanigawa, Hiroshima, JP;
Hiroaki Toguchi, Okazaki, JP;
Naoki Hirakawa, Kawasaki, JP;
Takashi Ishiguro, Takasaki, JP;
Masayuki Sato, Takasaki, JP;
Tetsuo Hironaka, Hiroshima, JP;
Kazuya Tanigawa, Hiroshima, JP;
Hiroaki Toguchi, Okazaki, JP;
Naoki Hirakawa, Kawasaki, JP;
Takashi Ishiguro, Takasaki, JP;
Masayuki Sato, Takasaki, JP;
Taiyo Yuden Co., Ltd., Tokyo, JP;
Abstract
FPGAs and MPLDs, which are conventional programmable semiconductor devices, have had poor cost performance and did not suitably take long signal lines into account. To solve this, a flip-flop is built into each MLUT block comprised of a plurality of MLUTs, each MLUT comprising a memory and an address-data pair. With respect to the adjacent line between adjacent MLUTs, alternated adjacent line are introduced, while in the case of interconnects between non-adjacent MLUTs, dedicated distant line and, furthermore, a torus interconnect network are provided.