The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 09, 2012

Filed:

Apr. 05, 2006
Applicants:

Piermario Repetto, Turin, IT;

Sabino Sinesi, Turin, IT;

Sara Padovani, Turin, IT;

Stefano Bernard, Turin, IT;

Denis Bollea, Turin, IT;

Davide Capello, Turin, IT;

Alberto Pairetti, Udine, IT;

Michele Antonipieri, Udine, IT;

Inventors:

Piermario Repetto, Turin, IT;

Sabino Sinesi, Turin, IT;

Sara Padovani, Turin, IT;

Stefano Bernard, Turin, IT;

Denis Bollea, Turin, IT;

Davide Capello, Turin, IT;

Alberto Pairetti, Udine, IT;

Michele Antonipieri, Udine, IT;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/18 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabrication of transparent LED devices, of the type comprising the operations of: i) providing a series of conductive paths on a transparent underlayer; ii) connecting said conductive paths to electronic control means; iii) associating to said underlayer an array of LED sources addressable individually or in groups through said conductive paths, in which i) said LED sources are integrated in the form of chips, i.e., of elements obtained by dividing up a semiconductor wafer and without package, via technologies of the chip-on-board type; ii) said method envisages the use of the flip-chip technique for die bonding, i.e., the electrical connection of the chip to the underlayer.


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