The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Sep. 29, 2006
Atul Joshi, Thousand Oaks, CA (US);
Angelika Kononenko, Newbury Park, CA (US);
David J. Chiaverini, Irvine, CA (US);
Gananath Wijeratne, Thousand Oaks, CA (US);
John C. Stevens, Northridge, CA (US);
Selim Eminoglu, Camarillo, CA (US);
William E. Tennant, Thousand Oaks, CA (US);
Atul Joshi, Thousand Oaks, CA (US);
Angelika Kononenko, Newbury Park, CA (US);
David J. Chiaverini, Irvine, CA (US);
Gananath Wijeratne, Thousand Oaks, CA (US);
John C. Stevens, Northridge, CA (US);
Selim Eminoglu, Camarillo, CA (US);
William E. Tennant, Thousand Oaks, CA (US);
Teledyne Scientific & Imaging, LLC, Thousand Oaks, CA (US);
Abstract
Embodiments of a read-out integrated circuit (ROIC) include a plurality of unit cells. Each unit cell includes a bias subsystem, a reset switch, at least one integration capacitor, and at least one read switch. A focal plane array includes a plurality of photo detectors disposed in a grid and a ROIC. A column buffer includes a first buffer subsystem, a feedback subsystem, a first and second correlated double sampling subsystem, and a second buffer subsystem. A ROIC includes at least one integration subsystem having a transistor subsection, a poly silicon layer, and a plurality of active layer sections.