The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 09, 2012
Filed:
Sep. 16, 2011
Tae-hyun Kim, Suwon-si, KR;
Kyung-hyun Kim, Seoul, KR;
Jae-hwang Sim, Seoul, KR;
Jae-jin Shin, Seoul, KR;
Jong-heun Lim, Seoul, KR;
Hyun-min Park, Suwon-si, KR;
Tae-Hyun Kim, Suwon-si, KR;
Kyung-Hyun Kim, Seoul, KR;
Jae-Hwang Sim, Seoul, KR;
Jae-Jin Shin, Seoul, KR;
Jong-Heun Lim, Seoul, KR;
Hyun-Min Park, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
A method of manufacturing a semiconductor device includes forming a plurality of preliminary gate structures, forming a capping layer pattern on sidewalls of the plurality of preliminary gate structures, and forming a blocking layer on top surfaces of the plurality of preliminary gate structures and the capping layer pattern such that a void is formed therebetween. The method also includes removing the blocking layer and an upper portion of the capping layer pattern such that at least the upper sidewalls of the plurality of preliminary gate structures are exposed, and a lower portion of the capping layer pattern remains on lower sidewalls of the preliminary gate structures. The method further includes forming a conductive layer on at least the upper sidewalls of the plurality of preliminary gate structures, reacting the conductive layer with the preliminary gate structures, and forming an insulation layer having an air gap therein.