The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Feb. 11, 2011
Ying-tsai Chang, Fremont, CA (US);
Hwa Mao, Taipei, TW;
Swey-yan Shei, Cupertino, CA (US);
Ming-yang Wang, Lafayette, CA (US);
Yu-chin Hsu, Cupertino, CA (US);
Ying-Tsai Chang, Fremont, CA (US);
Hwa Mao, Taipei, TW;
Swey-Yan Shei, Cupertino, CA (US);
Ming-Yang Wang, Lafayette, CA (US);
Yu-Chin Hsu, Cupertino, CA (US);
SpringSoft, Inc., Hsinchu, TW;
SpringSoft USA, Inc., San Jose, CA (US);
Abstract
Methods and systems for testing a design under verification (DUV), the method including receiving, at an interface, configured Field Programmable Gate Array (FPGA) images and runtime control information, wherein each of the FPGA images contains a respective portion of the DUV, and a respective verification module associated with a respective FPGA device. The method further includes, sending, by the interface, each of the FPGA images to each of the respective FPGA devices associated with each of the respective FPGA images. The method also includes, sending, by the interface, timing and control information to each of the respective verification modules based on runtime control information received from the host workstation. In response to receiving timing and control information, each of the respective verification modules, controls each of the respective portions of the DUV in each of the respective FPGA devices.