The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Aug. 27, 2010
Patrick G. Drennan, Gilbert, AZ (US);
Ryan Silk, Saskatoon, CA;
Joel Cooper, Saskatoon, CA;
Jeffrey Dyck, Saskatoon, CA;
Samer Sallam, Saskatoon, CA;
Trent Lome Mcconaghy, Vancouver, CA;
Patrick G. Drennan, Gilbert, AZ (US);
Ryan Silk, Saskatoon, CA;
Joel Cooper, Saskatoon, CA;
Jeffrey Dyck, Saskatoon, CA;
Samer Sallam, Saskatoon, CA;
Trent Lome McConaghy, Vancouver, CA;
Solido Design Automation Inc., Saskatoon, CA;
Abstract
A method for proximity-aware circuit design where a set of layout constraint values that satisfy predetermined performance or yield goals is determined in accordance with a layout effect model. One of the layout constraint values is then selected as a constraint input to layout design, and a design layout is performed with the selected layout constraint value to provide a semiconductor circuit design for the semiconductor circuit. The set of layout constraint values can be determined by varying an instance parameter of the layout effect model to determine a set of instance parameters that satisfy the at least one predetermined performance or yield goal in accordance with the layout effect model, and determining layout constraints associated with each instance parameter of the set of instance parameters, thus providing a number of candidates in a design space that can be evaluated according to performance and/or yield tradeoffs.