The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Oct. 23, 2006
Hendrikus Petrus Elisabeth Vranken, Weert, NL;
Hendrikus Petrus Elisabeth Vranken, Weert, NL;
NXP B.V., Eindhoven, NL;
Abstract
A method () for locating a fault in an integrated circuit () having a plurality of digital outputs coupled to compaction logic () in a test mode of the integrated circuit, the compaction logic comprising at least one output for providing a test response is disclosed. The method comprises the steps of: providing a simulation model of the integrated circuit (); providing the simulation model with a plurality of test patterns (); receiving a plurality of simulated test responses to said test patterns (); defining a plurality of bits in the plurality of responses, said bits defining a signature of the fault (); providing the integrated circuit with a further plurality of test patterns (); receiving a plurality of test responses to said further plurality of test patterns (); and checking the plurality of responses for the presence of the signature (). This method provides improved fault detectability for an IC subjected thereto.