The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Apr. 30, 2008
James D. Whitfield, Gilbert, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Abhijat Goyal, Chandler, AZ (US);
Rouying Zhan, Gilbert, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Chai Ean Gill, Chandler, AZ (US);
Abhijat Goyal, Chandler, AZ (US);
Rouying Zhan, Gilbert, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
An electrostatic discharge (ESD) clamp (), coupled across input-output (I/O) () and common (GND) () terminals of a protected semiconductor SC device or IC (), comprises, an ESD transistor (ESDT) () with source-drain () coupled between the GND () and I/O (), a first resistor () coupled between gate () and source () and a second resistor () coupled between ESDT body () and source (). Paralleling the resistors () are control transistors () with gates () coupled to one or more bias supplies Vb, Vb'. The main power rail (Vdd) of the device or IC () is a convenient source for Vb, Vb′. When the Vdd is off during shipment, handling, equipment assembly, etc., the ESD trigger voltage Vtis low, thereby providing maximum ESD protection when ESD risk is high. When Vdd is energized, Vtrises to a value large enough to avoid interference with normal circuit operation but still protect from ESD events. Parasitic leakage through the ESDT () during normal operation is much reduced.