The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Apr. 29, 2009
Carl V. Thompson, Acton, MA (US);
Tongjai Chookajorn, Cambridge, MA (US);
Carl V. Thompson, Acton, MA (US);
Tongjai Chookajorn, Cambridge, MA (US);
Massachusetts Institute of Technology, Cambridge, MA (US);
Abstract
Embodiments of an on-chip interconnect having a multilevel reservoir are provided. In general, the on-chip interconnect is an interconnect within an integrated circuit and includes an interconnect segment and a multilevel reservoir. The interconnect segment has an anode end and a cathode end. The multilevel reservoir is adjacent to the cathode end of the interconnect segment and operates as a reservoir of metal atoms. As such, any electromigration-induced void begins forming in the multilevel reservoir rather than the cathode end of the interconnect segment. As a result, a reliability of the on-chip interconnect is substantially improved as compared to that of traditional on-chip interconnects. In addition, by utilizing multiple levels of the integrated circuit, a volume of the multilevel reservoir is substantially increased as compared to a volume of a corresponding single-level reservoir.