The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 02, 2012
Filed:
Feb. 02, 2011
Yeh-ning Jou, Linkou Township, Taipei County, TW;
Chia-wei Hung, Caotun Township, Nantou County, TW;
Hwa-chyi Chiou, Hsinchu, TW;
Yeh-jen Huang, Hsinchu, TW;
Shu-ling Chang, Hsinchu, TW;
Yeh-Ning Jou, Linkou Township, Taipei County, TW;
Chia-Wei Hung, Caotun Township, Nantou County, TW;
Hwa-Chyi Chiou, Hsinchu, TW;
Yeh-Jen Huang, Hsinchu, TW;
Shu-Ling Chang, Hsinchu, TW;
Vanguard International Semiconductor Corporation, Hsinchu, TW;
Abstract
An ESD protection structure is disclosed. A substrate comprises a first conductive type. A first diffusion region is formed in the substrate. A first doped region is formed in the first diffusion region. A second doped region is formed in the first diffusion region. A third doped region is formed in the substrate. A first isolation region is formed in the substrate, covers a portion of the first diffusion region and is located between the second and the third doped regions. A fourth doped region is formed in the substrate. When the first doped region is coupled to a first power line and the third and the fourth doped regions are coupled to a second power line, an ESD current can be released to the second power line from the first power line. During the release of the ESD current, the second doped region is not electrically connected to the first power line.