The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 25, 2012
Filed:
Sep. 18, 2009
Joachim Keinert, Altdorf, DE;
Douglass T. Lamb, Cary, NC (US);
David W. Lewis, Pleasant Valley, NY (US);
Shyam Ramji, Lagrangeville, NY (US);
Joachim Keinert, Altdorf, DE;
Douglass T. Lamb, Cary, NC (US);
David W. Lewis, Pleasant Valley, NY (US);
Shyam Ramji, Lagrangeville, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An automated method and apparatus for positioning gate array circuits in an integrated circuit design. An initial integrated circuit design includes logic cells and gate array fill circuits positioned thereon. The gate array fill circuits are positioned in available space between the adjacent logic cells so as to fill the available space with the maximum gate array fill circuits. A gate array logic element to be positioned in the integrated circuit design, such as may be required by an engineering change to the circuit design, is automatically positioned between adjacent logic cells so as to allow for full utilization of any space remaining between the adjacent logic cells by gate array fill circuits.