The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2012

Filed:

Mar. 02, 2009
Applicants:

Anatoli S. Andreev, Chassell, MI (US);

Olaf K. Hendrickson, Rochester, MN (US);

John M. Ludden, Essex Junction, VT (US);

Richard D. Peterson, Austin, TX (US);

Elena Tsanko, Haifa, IL;

Inventors:

Anatoli S. Andreev, Chassell, MI (US);

Olaf K. Hendrickson, Rochester, MN (US);

John M. Ludden, Essex Junction, VT (US);

Richard D. Peterson, Austin, TX (US);

Elena Tsanko, Haifa, IL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/44 (2006.01); G06F 13/10 (2006.01); G06F 9/45 (2006.01); G06F 9/26 (2006.01); G06F 9/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

A computer-implemented method, system and computer program product are presented for managing an Effective-to-Real Address Table (ERAT) and a Translation Lookaside Buffer (TLB) during test verification in a simulated densely threaded Network On a Chip (NOC). The ERAT and TLB are stripped out of the computer simulation before executing a test program. When the test program experiences an inevitable ERAT-miss and/or TLB-miss, an interrupt handler walks a page table until the requisite page for re-populating the ERAT and TLB is located.


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