The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2012

Filed:

Jun. 15, 2007
Applicants:

Zahid Hussain, Ascot, GB;

John Brothers, Calistoga, CA (US);

Jim Xu, San Jose, CA (US);

Inventors:

Zahid Hussain, Ascot, GB;

John Brothers, Calistoga, CA (US);

Jim Xu, San Jose, CA (US);

Assignee:

Via Technologies, Inc., Hsin-Tien, Taipei, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 7/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a graphics processing unit comprising an instruction decoder and sum-of-absolute-differences (SAD) accleration logic. The instruction decoder is configured to decode a SAD instruction into parameters describing an M×N and an n×n pixel block in U,V coordinates. The SAD accleration logic is configured to receive the parameters and compute SAD scores. Each SAD score corresponds to the n×n block and to one block contained within the M×N pixel block and horizontally offset within the n×n block. Also disclosed is a GPU comprising a host processor interface receiving video acceleration instructions and a video acceleration unit. The unit is responsive to the instructions and comprises SAD accleration logic configured to receive the parameters and compute SAD scores. Each SAD score corresponds to an n×n pixel block and to one block contained within an M×N block and horizontally offset within the n×n block. M, N, and n are integers.


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