The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 25, 2012

Filed:

Jan. 20, 2011
Applicants:

Yoshikazu Harada, Kanagawa-ken, JP;

Norihiro Fujita, Kanagawa-ken, JP;

Masaki Fujiu, Kanagawa-ken, JP;

Inventors:

Yoshikazu Harada, Kanagawa-ken, JP;

Norihiro Fujita, Kanagawa-ken, JP;

Masaki Fujiu, Kanagawa-ken, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/06 (2006.01);
U.S. Cl.
CPC ...
Abstract

A nonvolatile semiconductor memory device and a nonvolatile memory system having a unit which suppresses erroneous reading of a nonvolatile semiconductor memory device of a multi-level memory system are provided. In the nonvolatile semiconductor memory device and the nonvolatile memory system of the multi-level memory system, a first verify voltage is used when data is written before a packaging process, and the verify voltage is switched to a second verify voltage lower than the first verify voltage when data is written after the packaging process.


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