Compound field effect transistor with multi-feed gate and serpentine interconnect

Abstract

Aspects provide for reducing the size and cost of a compound semiconductor power FET device while increasing yield and maintaining current handling capabilities of the FET by distributing portions of the current in parallel to sections the source and drain fingers to maintain a low current density, and applying the gate signal to both ends of the gate fingers to increase yield. The current to be handled by the FET may be divided among a set of electrodes arrayed along the width of the source or drain fingers and oriented to cross the fingers along the length of the source and drain fingers. The current may be conducted from the electrodes to the source and drain fingers through vias disposed along the surface of the fingers. Heat developed in the source, drain, and gate fingers may be conducted through the vias to the electrodes and out of the device.