The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8271921 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 18, 2012

Filed:

Sep. 23, 2010
Applicants:

Izumi Nitta, Kawasaki, JP;

Yu Liu, Kawasaki, JP;

Inventors:

Izumi Nitta, Kawasaki, JP;

Yu Liu, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A set of pareto optimal solutions that are non-dominated solutions in a solution specification space for respective items in requirement specification is extracted with a combination of a circuit configuration including a specific function and a process constraint condition. Furthermore, pareto optimal solutions are extracted for all combinations of the circuit configuration and the process constraint condition, and pareto optimal solutions are extracted for the respective process constraint conditions. When such extracted data is distributed to designers, it is possible to reduce time to generate the pareto optimal solutions, and the designers can design the optimum circuit having a desired function by using such extracted data.


Find Patent Forward Citations

Nitta, Izumi. (2012). Automatic circuit design technique using pareto optimal solutions (U.S. Patent No. 8271921). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8271921

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