Delay locked loop circuit and semiconductor device having the delay locked loop circuit

Abstract

A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a delay circuit and a phase adjusting circuit. The phase adjusting circuit is configured to receive a clock signal output from the delay circuit, pass the clock signal through a N-divider and a replica path to create a N-divided delay signal, and detect phase information about an external clock signal in response to a rising edge and a falling edge of the N-divided delay signal, wherein N denotes a natural number. The delay circuit is configured to output the clock signal by adjusting a phase of the external clock signal in response to a result of the detection. A semiconductor device, semiconductor system, and method are also disclosed.