The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 18, 2012

Filed:

Dec. 13, 2010
Applicants:

Charles Razzell, Pleasanton, CA (US);

Hong Sair Lim, Singapore, SG;

Batuhan Okur, Singapore, SG;

Jerome Tjia, Singapore, SG;

Tue Fatt David Wee, Singapore, SG;

Inventors:

Charles Razzell, Pleasanton, CA (US);

Hong Sair Lim, Singapore, SG;

Batuhan Okur, Singapore, SG;

Jerome Tjia, Singapore, SG;

Tue Fatt David Wee, Singapore, SG;

Assignee:

ST-Ericsson SA, Plan-les-Ouates, CH;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 17/16 (2006.01); H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

A current boost circuit acts as an 'eye opener' for a digital bus line. A controlled current injects a fraction of the normal signaling current magnitude from a source driver onto the bus line, after a transition between the two logical states on the bus line is detected. The duration of the additional current injection is a fraction of the unit interval. In one embodiment, a linear system uses the summation of a proportional boost current and a delayed and negated proportional boost current. In another embodiment, a positive or negative edge detection circuit triggers a monostable pulse generator that controls the injection of short bursts of additional current into the bus lines. In some embodiments the boost current is suppressed when the bus line is driven from a driver other than the source driver.


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