The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2012
Filed:
Jun. 18, 2008
Bang-thu Nguyen, Santa Clara, CA (US);
Yan Wang, San Jose, CA (US);
Hong-tsz Pan, Cupertino, CA (US);
Xin Wu, Fremont, CA (US);
Bang-Thu Nguyen, Santa Clara, CA (US);
Yan Wang, San Jose, CA (US);
Hong-tsz Pan, Cupertino, CA (US);
Xin Wu, Fremont, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
An integrated circuit device layout and a method for detecting mask data handling errors are disclosed in which integrated circuit device layout includes a device region in which operable circuitry is disposed. Integrated circuit device layout also includes a verification region in which verification elements are disposed. The verification elements include cells that are duplicates of at least some of the different types of cells in device region and can include structures that are duplicates of at least some of the types of structures in the device region. The patterns in verification region are used in the final verification process to identify mask data handling errors in a mask job deck. Because the patterns in verification region are easy to locate and identify, the time required to perform the final verification process is reduced and the chance of error in the final verification process is reduced.