Memory device including a memory block having a fixed latency data output

Abstract

A memory block includes a memory circuit and a clock generation unit. The memory circuit may output read data in response to being clocked by a clock signal having a selectable delay that may be dependent upon a time taken for the read data to be output by a memory core after the read command is received at the memory block. The clock generation unit may cause the read data to be provided as an output of the memory block in response to being clocked by a selected data clock signal. The data clock signal may be selected from one of several clock edges generated by one of several clock edges of a system clock such that regardless of the frequency of the system clock, the read data is provided by the memory block a predetermined amount of time after the read command is received at the memory block.