The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 11, 2012

Filed:

Oct. 15, 2009
Applicants:

Hem C. Neema, Sunnyvale, CA (US);

Chi Bun Chan, San Jose, CA (US);

Kumar Deepak, San Jose, CA (US);

Nabeel Shirazi, Saratoga, CA (US);

Inventors:

Hem C. Neema, Sunnyvale, CA (US);

Chi Bun Chan, San Jose, CA (US);

Kumar Deepak, San Jose, CA (US);

Nabeel Shirazi, Saratoga, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Co-simulation platforms generally include a software-based system and a hardware-based system in which different portions of the circuit design are either simulated in a software-based system or emulated on a hardware-based system. Before a model of circuit design can be co-simulated, the circuit design must be transformed and configured into a form that can execute and interface with a specific hardware-based system. The embodiments of the present invention provide a method, system, and article of manufacture for co-simulation of a portion of a circuit design and achieve an advance in the art by improving co-simulation configuration and setup and providing co-simulation adjustment capabilities during runtime.


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