The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2012
Filed:
Aug. 27, 2009
Hidefumi Nawata, Kanagawa-ken, JP;
Kikuko Sugimae, Kanagawa-ken, JP;
Akihiro Kajita, Kanagawa-ken, UA;
Takamichi Tsuchiya, Mie-ken, JP;
Hidefumi Nawata, Kanagawa-ken, JP;
Kikuko Sugimae, Kanagawa-ken, JP;
Akihiro Kajita, Kanagawa-ken, UA;
Takamichi Tsuchiya, Mie-ken, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.