The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 11, 2012
Filed:
Aug. 04, 2010
Se-young Lee, Suwon-si, KR;
Il-young Yoon, Hwaseong-si, KR;
Boung-ju Lee, Suwon-si, KR;
Samsung Electronics Co., Ltd., Suwon-Si, Gyeonggi-Do, KR;
Abstract
An embedded semiconductor device which a logic region and the memory region are planarized with planarization resistance patterns and a method of manufacturing the same are disclosed. The embedded semiconductor device includes a substrate, gates formed on the substrate, source/drain regions formed on both sides of the gates in the substrate, a first interlayer dielectric (ILD) layer which covers the gates and the source/drain regions, first via plugs which vertically penetrate the first ILD layer and are selectively connected to the source/drain regions, capacitors and second via plugs selectively connected to the first via plugs, a second ILD layer that fills the space between the capacitors and the second via plugs, planarization resistance patterns formed on the second ILD layer, a third ILD layer formed on the second ILD layer and the planarization resistant patterns, and third via plugs which vertically penetrate the third ILD layer, and are selectively connected to a top electrode of the capacitors and the second via plugs.