The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2012

Filed:

Jan. 06, 2010
Applicants:

Satoru Funaki, Hitachi, JP;

Yasuhiro Kiyofuji, Hitachi, JP;

Masashi Suenaga, Hitachi, JP;

Shin Kokura, Hitachi, JP;

Eiji Kobayashi, Hitachinaka, JP;

Akihiro Onozuka, Hitachi, JP;

Yusuke Seki, Hitachi, JP;

Toshiki Shimizu, Hitachi, JP;

Yukiko Tahara, Hitachi, JP;

Yuta Sugimoto, Hitachi, JP;

Inventors:

Satoru Funaki, Hitachi, JP;

Yasuhiro Kiyofuji, Hitachi, JP;

Masashi Suenaga, Hitachi, JP;

Shin Kokura, Hitachi, JP;

Eiji Kobayashi, Hitachinaka, JP;

Akihiro Onozuka, Hitachi, JP;

Yusuke Seki, Hitachi, JP;

Toshiki Shimizu, Hitachi, JP;

Yukiko Tahara, Hitachi, JP;

Yuta Sugimoto, Hitachi, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A failure is detected immediately and certainly, and continuation of processing in an unstable state is prevented. A first error detection code is generated from first information which is output as a result of execution of a predetermined program conducted by a first processor. A second error detection code is generated from second information which is output as a result of execution of the program conducted by a second processor which is configured so as to output the same computation result as that of the first processor. It is detected whether the first information is the same as the second information, and it is detected whether the first error detection code is the same as the second error detection code. Writing the first information or the second information into a main memory is controlled on the basis of a result of the detection.


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