The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2012
Filed:
Oct. 28, 2005
Myron J. Miske, Newfields, NH (US);
Myron J. Miske, Newfields, NH (US);
Fairchild Semiconductor Corporation, San Jose, CA (US);
Abstract
An ESD protection circuit is described that protects the output transistors of a target circuit, usually an integrated circuit, that has an output enable, OE, or similar control input. An OE signal turns off the output transistors allowing the target circuit output, or outputs, to electrically float. Such a condition is commonly called a three state condition. The inventive protection circuit is not connected to the output directly, it senses an ESD voltage spike at the +Vdd contact to the circuit and produces a timed signal. The timed signal is converted to logic levels and gated with the OE signal (that the system previously provided to the OE control input). The output of gate forms a new OE control input signal that forces the target circuit into its three state condition during the period of the timed signal.