Clock generating circuit

Abstract

According to one embodiment, a clock generating circuit includes first and second current generating circuits, first and second voltage generating circuits, first and second comparing circuits, a clock output circuit, a control circuit. The first current generating circuit is configured to generate a first current. The first voltage generating circuit is configured to generate a first voltage which increases or decreases according to a phase of a clock signal as time advances by the first current. The first comparing circuit is configured to compare the first voltage with a first threshold voltage to generate a first comparison result. The second current generating circuit is configured to generate a second current. The second comparing circuit is configured to compare the second voltage with a second threshold voltage to generate a second comparison result. The clock output circuit is configured to generate the clock signal whose phase inverts in synchronization with timing when the first and the second comparison results change. The control circuit is configured to generate a random number and configured to variably control at least one of the first current, the second current, the first threshold voltage and the second threshold voltage according to the random number.