The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 28, 2012

Filed:

Jun. 29, 2010
Applicants:

Fumio Yuki, Fujimino, JP;

Hiroki Yamashita, Hachioji, JP;

Koji Fukuda, Huchu, JP;

Inventors:

Fumio Yuki, Fujimino, JP;

Hiroki Yamashita, Hachioji, JP;

Koji Fukuda, Huchu, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 3/017 (2006.01);
U.S. Cl.
CPC ...
Abstract

There is provided a waveform equalization circuit with pulse width modulation that includes pulse-width adjust-level generation circuits PWCLC, PWCLC, for generating a pulse-width adjust-level VCNT on the basis of preceding input data units Din_P, Din_N, respectively, pulse-width adjustment circuits PWCC, PWCC, for adjusting a pulse-width according to VCNT, respectively, and a waveform shaping circuit WAC for shaping a waveform of an output signal from each of the pulse-width adjustment circuits. The pulse-width adjustment circuit has a driving power to be controlled according to a consecutive bits count of each of the preceding input data units, and varies transition time of each of output data units Do_P, Do_N, thereby adjusting the pulse width. With the use of such a waveform equalization scheme as above, it is possible to attain reduction in power consumption due to simplification in circuit configuration, and further, use of CMOS circuits will enable power consumption to be held back to a low level.


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