The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 28, 2012
Filed:
Mar. 31, 2009
James D. Whitfield, Gilbert, AZ (US);
Changsoo Hong, Phoenix, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Changsoo Hong, Phoenix, AZ (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
Electrostatic discharge (ESD) protection clamps () for I/O terminals () of integrated circuit (IC) cores () comprise a bipolar transistor () with an integrated Zener diode () coupled between the base () and collector () of the transistor (). Prior art variations () in clamp voltage in different parts of the same IC chip or wafer caused by prior art deep implant geometric mask shadowing are avoided by using shallow implants () and forming the base () coupled anode () and collector () coupled cathode () of the Zener () using opposed edges () of a single relatively thin mask (). The anode () and cathode () are self-aligned and the width () of the Zener space charge region () therebetween is defined by the opposed edges () substantially independent of location and orientation of the ESD clamps () on the die or wafer. Because the mask () is relatively thin and the anode () and cathode () implants () relatively shallow, mask shadowing is negligible and prior art clamp voltage variations () are avoided.