The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
Nov. 04, 2010
Vinay Verma, Fremont, CA (US);
Gitu Jain, Los Gatos, CA (US);
Sanjeev Kwatra, Cupertino, CA (US);
Taneem Ahmed, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Vinay Verma, Fremont, CA (US);
Gitu Jain, Los Gatos, CA (US);
Sanjeev Kwatra, Cupertino, CA (US);
Taneem Ahmed, Toronto, CA;
Sandor S. Kalman, Santa Clara, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.