The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
Oct. 09, 2009
Susumu Kobayashi, Kanagawa, JP;
Susumu Kobayashi, Kanagawa, JP;
Renesas Electronics Corporation, Kawasaki-Shi, Kanagawa, JP;
Abstract
A designing apparatus includes an initial estimating portion, a general power supply noise analyzing portion, a layout designing portion, a detail estimating portion, a detail power supply noise analyzing portion, and a layout adjusting portion. The initial estimating portion estimates general values of an entire consumed current and an entire on-chip capacitance. Based on the estimated general values, the general power supply noise analyzing portion creates a lumped constant circuit model so as to conduct a power supply noise analysis, for computing a current-capacitance ratio. Based on the current-capacitance ratio, the layout designing portion performs placement of cells for each of predetermined regions obtained by dividing a placement region. The detail estimating portion creates a lumped constant circuit model for each of the predetermined regions so as to estimate detail values of the consumed current and the on-chip capacitance for each of the predetermined regions. Based on the detail values, the detail power supply noise analyzing portion conducts a detail power supply noise analysis. Based on a result of the detail power supply noise analysis, the layout adjusting portion performs adjustment of the placement of the cells.