The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8250504 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 21, 2012

Filed:

Sep. 10, 2009
Applicant:

Takashi Shikata, Kawasaki, JP;

Inventor:

Takashi Shikata, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A designing method of a semiconductor integrated circuit is provided, the method including a preparation step of preparing first design data having a power gating circuit for supplying a power supply voltage to a logic circuit according to a power gating control signal and a first clamp circuit for clamping an output signal from the logic circuit according to a clamp control signal; and a generation step of generating, in order to verify the first design data, second design data in which a first mask circuit for masking the output signal from the logic circuit according to the power gating control signal is added in place of the power gating circuit to the first design data.


Find Patent Forward Citations

Shikata, Takashi. (2012). Designing method of semiconductor integrated circuit (U.S. Patent No. 8250504). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8250504

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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