Automated synthesis apparatus and method

Abstract

Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation. At such time the bits of component 1's of valid bits of the GVC of the inside resolved condition are masked in the bitwise logical OR operation, and parallel IF statements are treated the same as speculative execution of a condition.