The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 8250414 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 21, 2012

Filed:

Feb. 29, 2008
Applicant:

Andreas-juergen Rohatschek, Wernau/Neckar, DE;

Inventor:

Andreas-Juergen Rohatschek, Wernau/Neckar, DE;

Assignee:

Robert Bosch GmbH, Stuttgart, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11B 20/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A device has at least one integrated signal path having a measurable asymmetrical signal lag and/or jitter, an output signal of the integrated signal path being able to be decoupled in a first measuring operating mode using a controllable integrated multiplexer to measure an asymmetrical signal lag of a measuring path, which includes the integrated signal path and the integrated multiplexer, and a measuring signal being able to be decoupled in a second measuring operating mode using the controllable integrated multiplexer to measure the asymmetrical signal lag of the integrated multiplexer.


Find Patent Forward Citations

Rohatschek, Andreas-Juergen. (2012). Method for determining an asymmetrical signal lag of a signal path inside an integrated circuit (U.S. Patent No. 8250414). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/8250414

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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