The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 21, 2012

Filed:

Feb. 18, 2010
Applicants:

Jianhua Ju, Shanghai, CN;

Xianjie Ning, Shanghai, CN;

Inventors:

Jianhua Ju, Shanghai, CN;

Xianjie Ning, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2011.01);
U.S. Cl.
CPC ...
Abstract

The present invention discloses a rapid thermal annealing method for a semiconductor device, which includes the steps of: establishing a ternary correspondence relationship among a device electrical parameter, an annealing temperature, and an STI distribution density; deriving an STI distribution density in a specific area of the semiconductor device and a target STI distribution density; determining whether the STI distribution density in the specific area is larger than the target STI distribution density; if the STI distribution density in the specific area is larger than the target STI distribution density, adding a virtual structure in the specific area to make the STI distribution density in the specific area equal to the target STI distribution density; and deriving from the ternary correspondence relationship a target annealing temperature corresponding to the target STI distribution density and performing an annealing process with the annealing temperature on the semiconductor device to achieve a target electrical parameter. The method can alleviate the phenomenon of temperature non-uniformity of a rapid thermal annealing process so as to avoid any influence thereof upon the electrical performance of the semiconductor device.


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