The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
May. 25, 2010
Vinod Jain, Noida, IN;
Deependra K. Jain, Jabalpur, IN;
Krishna Thakur, Greater Noida, IN;
Avinish Chandra Tripathi, Noida, IN;
Sanjay Kumar Wadhwa, Noida, IN;
Vinod Jain, Noida, IN;
Deependra K. Jain, Jabalpur, IN;
Krishna Thakur, Greater Noida, IN;
Avinish Chandra Tripathi, Noida, IN;
Sanjay Kumar Wadhwa, Noida, IN;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A duty cycle correction circuit for correcting the duty cycle of a clock signal generated by a clock generator includes a complementary buffer chain, level shifter circuits and a self-bias circuit. A clock signal with a distorted duty cycle and its complement are provided to the level shifter circuits. The level shifter circuits reduce the magnitude of voltage of the clock signal and the complement and generate level shifted signals. The level shifted signals are provided to a differential amplifier that generates a control signal indicating the magnitude of distortion in the duty cycle. The control signal is used to correct the duty cycle of the clock signal. The self-bias circuit is used to bias the differential amplifier.