Comparator with offset compensation, in particular for analog digital converters

Abstract

A comparator formed by first and second stages. The second stage is formed by a pair of output transistors connected between a power-supply line and respective output nodes; a pair of bias transistors, connected between a respective output node and a current source; a pair of memory elements, connected between the control terminals of the output transistors and opposite output nodes; and switches coupled between the control terminals of the respective output transistors and the respective output nodes. In an initial autozeroing step, the first stage stores its offset so as to generate an offset-free current signal. In a subsequent tracking step, the second stage receives the current signal and the memory elements store control voltages of the respective output transistors. In a subsequent evaluating step, the first stage is disconnected from the second stage and the memory elements receive the current signal and switch the first and the second output node depending on the current signal. In subsequent comparisons, the tracking and evaluating steps follow one another without performing the autozeroing step.