The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 21, 2012
Filed:
Mar. 03, 2009
Takuo Kaitoh, Mobara, JP;
Hidekazu Miyake, Mobara, JP;
Takeshi Sakai, Kokubunji, JP;
Terunori Saitou, Mobara, JP;
Takuo Kaitoh, Mobara, JP;
Hidekazu Miyake, Mobara, JP;
Takeshi Sakai, Kokubunji, JP;
Terunori Saitou, Mobara, JP;
Hitachi Displays, Ltd., Chiba-ken, JP;
Panasonic Liquid Crystal Display Co., Ltd., Hyogo-Ken, JP;
Abstract
In a bottom-gate-type thin film transistor used in a liquid crystal display device in which a poly-Si layer and an a-Si layer are stacked, a quantity of an ON current which flows in the thin film transistor can be increased. A poly-Si layer and an a-Si layer are stacked on a gate electrode as an active layer by way of a gate insulation film therebetween in order of the poly-Si layer and the a-Si layer. An n+Si layer and a source/drain layer are formed on the a-Si layer thus forming a thin film transistor. A forward current which flows in the thin film transistor mainly flows in the poly-Si layer. To decrease contact resistance against the forward current between the poly-Si layer and the n+Si layer, an edge portion of the a-Si layer and an edge portion of the poly-Si layer assume a concavo-convex shape thus particularly increasing a contact area between the poly-Si layer and the n+Si layer whereby the contact resistance against the forward current can be decreased leading to the increase of a quantity of an ON current.