The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 14, 2012
Filed:
Jan. 05, 2009
Alexander Paley, Kfar-Saba, IL;
Sergey Anatolievich Gorobets, Edinburgh, GB;
Eugene Zilberman, Richmond Hill, CA;
Alan David Bennett, Edinburgh, GB;
Shai Traister, San Jose, CA (US);
Andrew Tomlin, San Jose, CA (US);
William S. Wu, Cupertino, CA (US);
Bum Suck SO, San Jose, CA (US);
Alexander Paley, Kfar-Saba, IL;
Sergey Anatolievich Gorobets, Edinburgh, GB;
Eugene Zilberman, Richmond Hill, CA;
Alan David Bennett, Edinburgh, GB;
Shai Traister, San Jose, CA (US);
Andrew Tomlin, San Jose, CA (US);
William S. Wu, Cupertino, CA (US);
Bum Suck So, San Jose, CA (US);
SanDisk Technologies Inc., Plano, TX (US);
Abstract
A portion of a nonvolatile memory is partitioned from a main multi-level memory array to operate as a cache. The cache memory is configured to store at less capacity per memory cell and finer granularity of write units compared to the main memory. In a block-oriented memory architecture, the cache has multiple functions, not merely to improve access speed, but is an integral part of a sequential update block system. The cache memory has a capacity dynamically increased by allocation of blocks from the main memory in response to a demand to increase the capacity. Preferably, a block with an endurance count higher than average is allocated. The logical addresses of data are partitioned into zones to limit the size of the indices for the cache.