The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 14, 2012

Filed:

Jul. 24, 2008
Applicants:

Masahiro Horiguchi, Tottori, JP;

Hideki Kaneko, Tottori, JP;

Shunichi Nakashima, Yazu, JP;

Hiroyuki Ito, Tottori, JP;

Inventors:

Masahiro Horiguchi, Tottori, JP;

Hideki Kaneko, Tottori, JP;

Shunichi Nakashima, Yazu, JP;

Hiroyuki Ito, Tottori, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display device includes a pair of substrates, a plurality of gate lines arranged in parallel, a plurality of common lines arranged in parallel, a plurality of source lines arranged in such a manner that the direction of the source lines intersects the direction of the gate lines and the common lines, thin-film transistors arranged in the vicinity of intersections of the gate lines and source lines, lower electrodes arranged in respective regions separated by the plurality of gate lines and the plurality of source lines, the lower electrodes being connected to the common lines and composed of a transparent conductive material, upper electrodes arranged on surfaces of the respective lower electrodes with an insulating film provided between the upper electrode and the lower electrode, each of the upper electrodes having a plurality of slits arranged in parallel with one another, the gate lines, the common lines, the source lines, the thin-film transistors, the lower electrodes, and upper electrodes being arranged on one of the pair of substrates, a liquid crystal layer arranged between the pair of substrates and driven by an electric field produced between the lower electrodes and the upper electrodes, and first conductive material layers arranged on surfaces of the common lines at intersections of the source lines and the common lines.


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